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数据率控制器
Depending on the state of the bit rate indication field, e.g. depending on whether the BRS field 714 corresponds to a recessive or a dominant bit, the data rate controller 410 may generate a corresponding output signal H/L (or change the level of the output signal H/L to a corresponding value) which is a precondition for the switching on of the third transistor 402 and the fourth transistor 406 which, when activated, provide the second current path which may only be used during the second data transmission mode.
The second data transmission mode may be initiated by the data rate controller 410 which monitors the stream of data to be transmitted TxD and, in dependence of the state of the bit rate indication field, may generate a corresponding data rate indicating signal H/L (or change the value thereof from a value indicating the operation in the first data transmission mode to a value indicating the operation in a second data transmission mode). The data rate indicating signal H/L may be processed by the logic AND-gate 404 and cause switching on (rendering conducting) the second current path which may thereby be involved into the process of signal generation.
As can be seen in FIG.A, the signal H/L which may be seen as a data rate indicating signal corresponding to the output signal 506 may be generated on the basis of the data TxD by the data rate controller 410 inside the transceiver 504 according to various embodiments. The data rate indicating signal H/L may be applied to and used within the transmitter circuit 502 according to various embodiments to switch its mode of other words, the data rate indicating signal H/L may specify, that the transmitter circuit 502 according to various embodiments is to be operated in the first data transmission mode or in the second data transmission mode.
The preconfigured bit rate which may be used to transmit data fields following the BRS field 714 and may be faster than the standard bit rate, as the arbitration phase is finished at preconfigured bit rate, if used at all, may be switched back automatically to the standard bit rate when a CRC (cyclic redundancy check) field (not shown in FIG.) is reached which follows the data field 722. The data rate controller 410 may be configured to detect a message integrity field, e.g. the CRC field, and alter the data rate signal H/L (e.g. change its bit value to the opposite value with respect to the value indicating the operation in the second data transmission mode) appropriately to cause the transmitter circuit 400 according to various embodiments to switch from the second data transmission mode to the first data transmission mode.
In the following it will be assumed that the data rate controller 410 detects during phase C a state of the bit rate indication field within the frame format of the message containing data TxD which indicates that data TxD (e.g. the part of the message following the bit rate indication field in the frame format of the message) is to be sent at the preconfigured data rate by the transmitter circuit 400 according to various embodiments. The bit rate indication field itself indicates, whether the part of the message following the bit rate indication field is to be transmitted at the standard bit rate or at the preconfigured bit the exemplary scenario shown in FIGS.A and 6B, at the end of phase C, i.e. at time t4, the transmitter circuit 400 according to various embodiments is switched into the second data transmission mode.
As already mentioned, the data rate controller 410 is responsible for detecting the state of the bit rate indication field, e.g. its bit value, within the frame format of the message containing data to be transmitted TxD by the transmitter circuit 410 according to various embodiments. In the CAN architecture, data to be transmitted TxD is transmitted via CAN messages which have a specified data frame format. In FIG. the standard format of a CAN FD message 700 is shown, i.e. a CAN message which may be transmitted at a flexible data rate.
The logic AND-gate 404 combines the output signal H/L from the data rate controller 410 with the data TxD currently being sent and outputs a corresponding signal which controls the third switch 402 and the fourth switch 406. In a sense, the data rate controller 410 and the logic AND-gate 404 may be seen to form a switching circuit which is configured to detect the state of a bit rate indication field and switch the data transmission mode of the transmitter circuit 400 according to various embodiments correspondingly, for example from the first data transmission mode into the second data transmission mode, when the bit rate indication field indicates that data TxD is to be sent at the preconfigured bit rate.
This may be achieved by switching off the first transistor 304 and the second transistor 312 and switching on the third transistor 402 and the fourth transistor 406. The third transistor 402 and the fourth transistor 406 which provide the second current path are only switched on in the second data transmission mode during the provision of a recessive bit by the transmitter circuit 400 according to various embodiments. The switching on of the third transistor 402 and the fourth transistor 406 in the second data transmission mode may be effectuated by a corresponding signal which is generated by data rate controller 410 upon detection of a corresponding state of a bit rate indication field within the data to be transmitted TxD by the transmitter circuit 400 according to various embodiments.
In step 904, the method may include switching the mode of operation of the transmitter circuit from the first data transmission mode to the second data transmission mode depending on the state of the bit rate indication field. The data rate controller 410 may be configured to read the bit rate indication field, e.g. the BRS field 714, within the CAN FD message 700 which is received at the input 316 of the transmitter circuit 400 according to various embodiments.
In the embodiments of the communication circuit 500 shown in FIGS.A and 5B the controller 106 may be configured as a CAN controller, for example a CAN microcontroller. The data rate controller 410 may be configured as a CAN FD controller which, among other features, may be configured to detect whether a first part or the second part of a message frame of data TxD and be further configured to indicate to the transmitter circuit 502 according to various embodiments that the second part of the message data frame is to be sent in the second data transmission mode.
In any case, the data rate controller 410 is included in the transceiver 504 according to various embodiments as shown in FIG.A. Therefore, the controller 106 does not have to be altered, for example no additional terminals have to be provided, since the transceiver 504 according to various embodiments includes the data rate controller 410 and may be able to switch between the first data transmission mode and the second data transmission mode in an autonomous manner. In other words, the transceiver 504 according to various embodiments may not require external inputs in order to decide, whether the transceiver circuit 504 according to various embodiments is to operate in the first or second data transmission mode.
In FIG.A a communication circuit 500 according to various embodiments within a node 102 as illustrated in FIG. is shown including the controller 106 and the transceiver 504 according to various embodiments. The interior of the transceiver 504 according to various embodiments is shown in more detail. The transceiver 504 according to various embodiments includes the receiver circuit 204, the transmitter circuit 502 according to various embodiments and the data rate controller 410. Although the data rate controller 410 and the transceiver circuit 502 are illustrated as separate entities, they may just as well form one component as shown in FIG., where the data rate controller 410 is part of the transmitter circuit 400 according to various embodiments. The separate display is only for ease of illustration.
The data rate controller 410 is configured to determine whether data TxD is currently to be sent at a standard bit rate or at a preconfigured bit rate which may be faster than the standard bit data rate controller 410 may be configured to monitor or analyse the data TxD in order to detecting a state of a message field (also refe rred to as bit rate indication field) within the data TxD to be transmitted. Upon detecting the state of the bit rate indication field within a message (data) frame of the data TxD, the data rate controller 410 may be configured the transmitter circuit 400 to switch from the first data transmission mode into the second data transmission mode by outputting a corresponding output signal H/L to the logic AND-gate 404.
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Sinônimos e analogias para "data rate controller" em inglês