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patterning process
Exemplos para "patterning process"
With this configuration, processing becomes easy in the case of using lithography in a patterning process, and the voltage value of the voltage pulse for changing the resistance value of the resistance variable element can be lowered.
根据该结构，在图案化工艺中使用光刻法的情况下，加工容易，能够使得使电阻变化型元件的电阻值变化的电压脉冲的电压值较低。
In such a configuration, processing is facilitated when lithography is used in the patterning process, and thereby the voltage value of the voltage pulse which varies the resistance value of the resistance variable element can be lowered.
采用这种结构，在形成图案的处理中，使用平版印刷的情况下，容易加工，并可以降低使电阻变化型元件的电阻值变化的电压脉冲的电压值。
The structure facilitates manufacture of the variable resistance element using photolithography as a patterning process, thereby reducing a voltage value of a voltage pulse varying a resistance value of the variable resistance element.
通过该结构，在图案形成过程中使用光刻的情况下，容易加工，能够降低使电阻变化元件的电阻值变化的电压脉冲的电压值。
Although the wiring pattern connected to the TFT device in the display area generally exists around the IC chip mounted area, when the formed pattern of the wiring pattern layout and the stress absorption region 6 are arranged suitably so as not be irradiated by the laser beam, the stress absorption regions 6 can be formed either after the wiring patterning process or after the IC chip mounting process without causing any problem.
虽然在显示区域中连接到TFT装置的布线图案通常存在于IC芯片安装区域的周围，但是，当所形成的布线图案布局的图案和应力吸收区6布置合适，不会被激光束照射时，则应力吸收区6能够在布线图案化加工之后形成，或者在IC芯片安装处理之后形成，而不会产生任何问题。
We produce sacrificial layers in the lithographic patterning process, various dielectric materials and enabling hardmasks. Our silicon based anti-reflective coatings under photoresists facilitate patterning with KrF and ArF laser excimers (248 and 193nm). Our manufacturing excellence enables even sub 5ppb total trace metals which is a prerequisite for sub-10nm nodes.
Pibond生产用于最先进节点的光刻辅助材料，并提供可以简化三维集成电路工艺步数的辅助层材料。除了光刻图案化工艺中的牺牲层材料，我们还生产各种介电材料和使能硬掩模材料。我们的硅基涂层材料非常有益于准分子激光KrF和ArF（248和193nm）图案化。目前我们正在为未来的光刻工艺准备新的材料。卓越的制造技术使得我们能够把痕量金属总量控制在5ppb以下，这是制造最先进工艺节点的先决条件。
Outros resultados
NILT works with several LED companies and has great experience in making wafer sized NIL stamps or molds with sub-wavelenght dot patterns or photonic bandgap structures (PBG), used directly in a NIL process for patterning of LEDs or used as masters for making polymer NIL stamps. MICRO FLUIDICS
NILT与多家LED公司合作用纳米压印技术造出一般晶圆大小的模板，上面图形印有亚波长SUB-WAVELENGTH圆点图形或光子带隙结构PHOTONIC BANDGAP STRUCTURES，用作母模复制聚合物NIL工模，或直接印制图形化蓝宝石衬底PSS。 微流控 （MICRO FLUIDICS）
It controls our genetic patterning, our physical body, our predisposition to certain health conditions, our aging process, our metabolism and much more.
它控制我们的遗传基因模式、我们的肉体身体、达到某一个健康状况我们容易得病的体质、我们的衰老过程、我们的新陈代谢以及更多的地方。
The booster antenna in SmartFacing is manufactured using a dry process with the use of laser patterning and paper as the substrate.
SmartFacing 中的增益天线采用了激光图案和以纸张为基材的干法生产工艺。
Processing Lithography Lithography, patterning of the wafers, is a critical step in the semiconductor process.
平版印刷 平版印刷（即晶圆的图案形成）是半导体 制程中的一个关键步骤。
The manufacturing of TFT/LED technologies and storage media is structured in wafer cleaning and metallization steps, patterning and etching, mapped in typical applications such as process cooling water, neutralization and chemical distribution.
TFT/LED 技术和存储介质的制造过程包括晶片清洁，金属涂敷，模型塑造和蚀刻处理；可应用于冷却水，中和及化工分配等典型工序中。
For a wide variety of applications, e.g. those requiring finer resolution, the preferred process comprises screen printing a paste which further comprises a photoinitiator and a photohardenable monomer, photo-patterning the dried paste and firing the resulting patterned paste.
就多种应用而言，例如彼等需要较精细分辨率者，较佳处理包括丝网印刷包含光起始剂及光可固化单体之膏、光图案化经亁燥之膏及烧制所得图案化之膏。
Likewise, a transparent conductive film made of ITO or the like is formed on the transparent substrate 37 configured of a glass substrate or a plastic film substrate Next, a resist layer is formed on an entire surface of the transparent conductive film, and then an electrode pattern is formed on the resist layer by patterning Then, the upper electrode 36 is formed by exposure and development, and the resist layer is removed Next, after an entire surface of the upper electrode 36 is coated with the alignment film 35, the alignment film 35 is dried and fired After that, a rubbing process is performed on the alignment film 35 Therefore, the alignment film 35 functions as an alignment film for horizontal alignment, and a pretilt is allowed to be formed in a rubbing direction of the alignment film 35
同样，在由玻璃衬底或塑料薄膜衬底构成的透明衬底37上形成由ITO等制成的透明导电薄膜。随后，透明导电薄膜的整个表面上形成抗蚀层，并通过图案形成在抗蚀层上形成电极图案。随后通过曝光和显影形成上电极36，并将抗蚀层去掉。接下来，在上电极36的整个表面上涂敷了取向膜35之后，对所述取向膜35进行干燥和燃烧。随后，对取向膜35进行摩擦过程。因此，所述取向膜35作为用于水平取向的取向膜，可在取向膜35的摩擦方向上形成预倾斜。
Subsequently, any deposit on the back side of the substrate due to the CVD growth process may be removed using plasma etch. A normal manufacturing process may also include patterning and etching of the emitter region or mesa 236, patterning and etching of the base region or mesa 234, and forming the junction termination region 260 at the periphery of the base mesa 234, such as illustrated in Figure 2. Outline of the base mesa 234 may advantageously have sufficiently rounded edges to prevent electric field concentration at its periphery. The junction termination region 260 is intended to prevent the device from electric field concentration at the periphery, thereby preventing early breakdown. The junction termination region 260 may be formed by a number of techniques, such as for example the junction termination extension technique. Further, a ring with an accurately controlled acceptor dose may be formed at the periphery of the base mesa 234 by implantation of boron or aluminum ions into the device periphery, the acceptor dose corresponding to full depletion of the implanted region at approximately 50 to 70% of the theoretical breakdown voltage. The dose may advantageously be in the range of approximately 0.9x1013 to 1.2x1013 cm-2 for electrically active acceptors in the JTE region.
随后，可利用等离子刻蚀消除CVD生长过程中在衬底的背面产生的任何沉积物。正常制造过程还可包括：对发射极区域或台面236进行图案形成和腐蚀；对基极区域或台面234进行图案形成和腐蚀；在基极台面234的外围形成结终端区域260，如图2所示。有利地，基极台面234的轮廓可具有足够圆的边缘，以防止其外围产生电场集中。所述结终端区域260用于防止装置外围产生电场集中，从而防止早期故障。所述结终端区域260可通过多种技术形成，例如，结终端延伸技术。进一步，可通过在装置外围植入硼或铝离子而在基极台面234的外围形成具有精确控制的受主剂量的环，受主剂量与理论击穿电压的约50至70%下植入区域的全耗尽剂量对应。有利地，对于JTE区域中的有源受主，所述剂量的范围可约为0.9x1013至1.2x1013 cm-2。
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Sinônimos e analogias para "patterning process" em inglês
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