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controller cache memory
Exemple pentru "controller cache memory"
Upgrading Controller Cache Memory
コントローラキャッシュメモリーのアップグレード
To Upgrade the Controller Cache Memory
コントローラキャッシュメモリーのアップグレード
Remove and Replace a Controller Cache Memory Card
コントローラのキャッシュメモリーカードの取り外しと交換
Alte rezultate
In response to indirect access instructions from the respective processors, the cache access controller accesses the cache memories other than the cache memory corresponding to the processor which has issued the indirect access instruction.
Some disk controllers with cache memory on board can sense a warm reboot, and flush any cached data to disk.
INFORMATION PROCESSOR, CACHE MEMORY CONTROLLER, AND MEMORY ACCESS SEQUENCE ASSURANCE METHOD
情報処理装置，キャッシュメモリ制御装置およびメモリアクセス順序保証方法
In addition, the systems have a CacheProtector feature which writes the contents of the RAID controller cache to flash memory if a power outage occurs.
The device controller comprises a cache memory for caching the data received from an application or a device driver and the data received from the target device and a control unit for transferring the data cached in the cache memory to the target device and the application or the device driver.
アプリケーションもしくはデバイスドライバから受信したデータ、ならびに前記対象デバイスから受信したデータをキャッシュするキャッシュメモリと、前記キャッシュメモリにキャッシュしたデータを前記対象デバイス、ならびに前記アプリケーションもしくはデバイスドライバ、に転送する制御部と、を備える。
A cache memory controller section comprises a plurality of STBs for holding eight-byte store data transmitted from a computing unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM.
キャッシュメモリ制御部は、演算器より送信された８バイトのストアデータを保持する複数のＳＴＢと、複数のＷＢと、ＤＡＴＡ－ＲＡＭと、ＦＣＤＲと、ＥＣＣ－ＲＡＭとを備える。
CACHE MEMORY CONTROLLER AND METHOD FOR CONTROLLING CACHE MEMORY
キャッシュメモリコントローラ及びキャッシュメモリコントロール方法
Provided is a cache memory controller (100) connected to a main memory (10) having an instruction area for storing a first program, and a data area for storing data used by instructions included in the first program, and to an access master (1) for executing instructions included in the first program, wherein the controller is provided with: a cache memory (110) for storing a portion of the data in the main memory (10); and a data processing unit (140) that, prior to execution of a specific instruction by the access master (1), and in accordance with transfer scheduling information contained in the beginning address of the specific instruction, calculates an access interval on the basis of the number of instruction steps remaining from the address of the instruction currently being executed by the access master (1), to the beginning address of the specific instruction; and during this access interval, transfers data to be used by the specific instruction from the main memory (10) to the cache memory (110).
第１のプログラムを格納する命令領域及び第１のプログラムに含まれる特定の命令で利用されるデータを格納するデータ領域を有するメインメモリ（１０）と、第１のプログラムに含まれている命令を実行するアクセスマスタ（１）と、に接続されたキャッシュメモリコントローラ（１００）であって、メインメモリ（１０）の一部のデータを格納するキャッシュメモリ（１１０）と、特定の命令の先頭アドレスを含む転送予約情報に従って、アクセスマスタ（１）が特定の命令を実行する前に、アクセスマスタ（１）で実行中の命令のアドレスから特定の命令の先頭アドレスまでの残りの命令ステップ数に基づいてアクセス間隔を算出し、このアクセス間隔で、特定の命令で利用されるデータをメインメモリ（１０）からキャッシュメモリ（１１０）に転送するデータ処理部（１４０）とを備える。
Each controller's cache memory could be expanded up to 32 GB, twice that of past models. The controllers supported dynamic cache residency (DCR), which continually keeps certain data in cache memory, so that the cache hit ratio for that data was always 100 percent.
The controller is configured with an unsupported cache memory size.
コントローラ のキャッシュメモリーサイズ構成はサポートされていません。
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