There is not enough occurrence buffer memory available. Possible causes include too many processors, too many filter threads, or the occurrence buffer is not being returned.
The track buffer memory controller 120 generates an acknowledge signal according to a predetermined priority order, in response to a memory access request signal from a buffer write controller 114, a buffer read controller 118, and a microcomputer I/F (intermediate frequency) part 122.
Intended enhancements of the above fundamental performance include, for example, increase of the capacity of a buffer memory, raise of the transfer rate attained by increasing the rotation speed, improvement of the performance of a channel coding LSI, a motor and so forth to shorten the rotation wait time, functional improvement of a servo circuit to shorten the seek time, and improvements of a head and disk media for realizing higher linear density recording.
If we want to use a buffer in a different queue (submit commands that reference this buffer to another queue), we need to specify buffer memory barrier that transitions buffer's ownership from one queue to another.
Reloading usually occurs on barriers. After modifying a buffer, we should set a buffer memory barrier, which will tell the driver that some operations influenced a buffer and it should be refreshed.
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