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output data buffer
Translation of "output data buffer" in Chinese
输出数据缓冲器
If the output data signal DOUTZ is at the high level, the pMOS transistor P7 is turned on and the nMOS transistor N7 is turned off to set the data terminal DQ to the high level. If the output data signal DOUTZ is at the low level, the pMOS transistor P7 is turned off and the nMOS transistor N7 is turned on to set the data terminal DQ to the low level. If supplied with the low-level output clock signal CLKOZ, the output data buffer 44 turns off the pMOS transistor P7 and the nMOS transistor N7 to set the data terminal DQ into the floating state. That is, while the read-out signal RDZ is L-level (inactive), the data terminal DQ becomes high impedance state, and while the read-out signal RDZ is H-level (active), the data terminal DQ becomes the same logic level as the output data signal DOUTZ.
ﾈ郢・所述输出数据信号DOUTZ处于高电平，所述pMOS晶体管P7ｴｪ｣ｬnMOS晶体管N7关闭，以将数据终端DQ设为高电平。ﾈ郢・所述输出数据信号DOUTZ处于低电平，所述pMOS晶体管P7ｹﾘｱﾕ｣ｬnMOS晶体管N7打开，以将数据终端DQ设为低电平。在被提供低电平输出时钟信号CLKOZ时，所述输出数据缓冲器44关闭pMOS晶体管P7ｺﾍnMOS晶体管N7｣ｬﾒﾔ将数据终端DQ设为浮动状态。即，所述读取信号RDZ为低电平（无源）时，所述数据终端DQ变为高阻抗状态，所述读取信号RDZ为高电平（有源）时，所述数据终端DQ变为与输出数据信号DOUTZﾏ猩ｬｵﾄ逻辑电平。
The output data buffer 44 has level shifters LSFT1 and LSFT2, a pMOS transistor P7 and an nMOS transistor N7 connected between the power supply line VDD and the ground line VSS, an NAND gate, and an NOR gate. The level shifter LSFT1 converts the high level of the output clock signal CLKOZ from the internal power supply voltage VIIR into the power supply voltage VDD. The level shifter LSFT2 converts the high level of the output data signal DOUTZ from the internal power supply voltage VIIC into the power supply voltage VDD.
所述输出数据缓冲器44具有电平位移器LSFT1ｺﾍLSFT2｡｢连接在电源线VDD与接地线VSS之间的pMOS晶体管P7ｺﾍnMOS晶体管N7｡｢与非门和或非门。所述电平位移器LSFT1将输出时钟信号CLKOZ的高电平从内部电源电压VIIR转换为电源电压VDD。所述电平位移器LSFT2将输出数据信号DOUTZ的高电平从内部电源电压VIIC转换为电源电压VDD。
The output data control unit 40 operates as it receives the internal power supply voltages VIIR and VIIC. The output data control unit 40 outputs a data signal output from the memory cell array 38 via a common data line CDBZ to the output data buffer 44 as an output data signal DOUTZ in a read operation mode. Further, the output data control unit 40 supplies the output data buffer 44 with an output clock signal CLKOZ which operates the output data buffer 44. An example of the output data control unit 40 is illustrated in FIG. 8.
The output data buffer 44 operates in the read operation mode, to output the output data signal DOUTZ to the data terminal DQ in response to the output clock signal CLKOZ. An example of the output data buffer 44 is illustrated in FIG. 8. The input data buffer 46 operates in the read operation mode, to output data received at the data terminal DQ to the input data control unit 42 as the input data DINZ.
所述输出数据缓冲器44在读取操作模式下运行，以响应输出时钟信号CLKOZｶ・将输出数据信号DOUTZ输出到数据终端DQ中。所述输出数据缓冲器44的一个示例如图8所示。所述输入数据换充其46在读取操作模式下运行，以将在数据终端DQ接收的数据输出到输入数据控制单元42中，作为输入数据DINZ｡｣
FIG. 8 illustrates an example of the output data control unit 40 and the output data buffer 44 illustrated in FIG. 2. FIG. 8 illustrates the output data control unit 40 and the output data buffer 44 corresponding to one data terminal DQ. The output data control unit 40 has a latency adjustment circuit CALADJ, a read clock buffer RCLKB, an output clock control circuit CLKCNT, a read data bus switch RDBSW, and an output data latch ODLT.
图8说明了图2所示的输出数据控制单元40和输出数据缓冲器44的示例。图8说明了与一个数据终端DQ对应的输出数据控制单元40和输出数据缓冲器44的示例。所述输出数据控制单元40具有演示调整电路CALADJ｡｢读取时钟缓冲器RCLKB｡｢输出时钟控制电路CLKCNT｡｢读取数据总线开关RDBSWｺﾍ输出数据锁存器ODLT｡｣
The read data bus switch RDBSW outputs the read data signal read to the common data line CDBZ to the output data latch circuit ODLT in a period when the read signal RDZ is at the high level (active). The output data latch circuit ODLT is the same as the command latch circuit CLAT illustrated in FIG. 7. The output data latch circuit ODLT receives the read data signal in the low-level period of the read clock signal RCLKZ, to latch the read data signal in synchronization with the leading edge of the read clock signal RCLKZ and output it as the output data signal DOUTZ to the output data buffer 44. The output data latch circuit ODLT latches the output of the common data line CDBZ in synchronized with the read out clock signal RCLKZ which changes H and L-level in burst length times.
所述读取数据总线开关RDBSW在读取信号RDZ处于高电平（有源）的阶段将读取到共用数据线CDBZｵﾄ读取数据信号输出到输出数据锁存电路ODLT中。所述输出数据锁存电路ODLTﾓ・图7所示的命令锁存电路CLAT相同。所述输出数据锁存电路ODLTﾔﾚ读取时钟信号RCLKZｵﾄｵﾍｵ酥ｽ阶段接收读取数据信号，以将读取数据信号与读取时钟信号RCLKZ的前沿同步锁存，并将其作为输出数据信号DOUTZ输出到输出数据缓冲器44中。所述输出数据锁存电路ODLT将共用数据线CDBZｵﾄ输出端与在突发长度时间内改变高低电平的读取时钟信号RCLKZ同步锁存。
The latency adjustment circuit CALADJ, the read clock buffer RCLKB, the read data bus switch RDBSW, and the output data latch ODLT operate in a period when the column internal power supply voltage VIIC is generated and stop operations in a period when the internal power supply voltage VIIC is not generated. The output clock control circuit CLKCNT operates as it receives the internal power supply voltage VIIR generated in a period except in the deep power-down mode. The output clock control circuit CLKCNT receives the low-level read signal RDZ in the period when the row internal power supply voltage VIIC is not generated, to set the output clock signal CLKOZ to the low level. The pMOS transistor P7 and the nMOS transistor N7 in the output data buffer 44 are turned off by the low-level output clock signal CLKOZ, so that the data terminal DQ becomes the high impedance state. Accordingly, it is possible to prevent the output data buffer 44 from malfunctioning when the latency adjustment circuit CALADJ, the read clock buffer RCLKB, the read data bus switch RDBSW, and the output data latch ODLT are stopped in operation.
所述等待时间调整电路CALADJ、读取时钟缓冲器RCLKB、读取数据总线开关RDBSW和输出数据锁存器ODLT在生成列内部电源电压VIIC的阶段运行，并在不生成列内部电源电压VIIC的阶段停止运行。所述输出时钟控制电路CLKCNT在接收深度低功耗模式之外的阶段生成的内部电源电压VIIR时运行。所述输出时钟控制电路CLKCNTﾔﾚｲｻﾉ嵭ﾉﾐﾐﾄﾚｲｿｵ釀ｴｵ醵ｹVIICｵﾄ阶段接收低电平读取信号RDZ，以将输出时钟信号CLKOZ设为低电平。所述输出数据缓冲器44中的pMOS晶体管P7和nMOS晶体管N7由低电平输出时钟信号CLKOZ关闭，使数据终端DQ变为高阻抗状态。由此，可ｷﾀﾖｹｵﾈｴﾊｱｼ莊遧酊ｷCALADJ｡｢读取时钟缓冲器RCLKB、读取数据总线开关RDBSW和输出数据锁存器ODLT停止运行时输出数据缓冲器44发生故障。
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