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data terminal dq
Vertaling van "data terminal dq" in Chinees
数据终端DQ
FIG. 8 illustrates an example of the output data control unit 40 and the output data buffer 44 illustrated in FIG. 2. FIG. 8 illustrates the output data control unit 40 and the output data buffer 44 corresponding to one data terminal DQ. The output data control unit 40 has a latency adjustment circuit CALADJ, a read clock buffer RCLKB, an output clock control circuit CLKCNT, a read data bus switch RDBSW, and an output data latch ODLT.
图8说明了图2所示的输出数据控制单元40和输出数据缓冲器44的示例。图8说明了与一个数据终端DQ对应的输出数据控制单元40和输出数据缓冲器44的示例。所述输出数据控制单元40具有演示调整电路CALADJ｡｢读取时钟缓冲器RCLKB｡｢输出时钟控制电路CLKCNT｡｢读取数据总线开关RDBSWｺﾍ输出数据锁存器ODLT｡｣
The input data control unit 42 has a write clock buffer WCLKB, an input data latch circuit IDLT, and a write data bus switch WDBSW. FIG. 7 illustrates the input data control unit 42 corresponding to one data terminal DQ (DINZ). The write clock buffer WCLKB generates a write clock signal WCLKZ in synchronization with the clock signal CLKZ when the write signal WRZ is activated at the high level. For example, the write clock signal WCLKZ is activated the number of clock cycles corresponding to a burst length.
所述输入数据控制单元42具有写入时钟缓冲器WCLKB｡｢输入数据锁存电路IDLTｺﾍ写入数据总线开关WDBSW｡｣图7说明了与一个数据终端DQ｣ｨDINZ｣ｩ对应的输入数据控制单元42。所述写入时钟缓冲器WCLKBﾔﾚ写入信号WRZｼ､ｻ鋙ｽ高电平时与时钟信号CLKZ同步生成写入时钟信号WCLKZ｡｣ﾀﾈ逎ｬ所述写入时钟缓冲器WCLKBｼ､ｻ・时，时钟周期的数量与突发长度对应。
The output data buffer 44 operates in the read operation mode, to output the output data signal DOUTZ to the data terminal DQ in response to the output clock signal CLKOZ. An example of the output data buffer 44 is illustrated in FIG. 8. The input data buffer 46 operates in the read operation mode, to output data received at the data terminal DQ to the input data control unit 42 as the input data DINZ.
所述输出数据缓冲器44在读取操作模式下运行，以响应输出时钟信号CLKOZｶ・将输出数据信号DOUTZ输出到数据终端DQ中。所述输出数据缓冲器44的一个示例如图8所示。所述输入数据换充其46在读取操作模式下运行，以将在数据终端DQ接收的数据输出到输入数据控制单元42中，作为输入数据DINZ｡｣
If the output data signal DOUTZ is at the high level, the pMOS transistor P7 is turned on and the nMOS transistor N7 is turned off to set the data terminal DQ to the high level. If the output data signal DOUTZ is at the low level, the pMOS transistor P7 is turned off and the nMOS transistor N7 is turned on to set the data terminal DQ to the low level. If supplied with the low-level output clock signal CLKOZ, the output data buffer 44 turns off the pMOS transistor P7 and the nMOS transistor N7 to set the data terminal DQ into the floating state. That is, while the read-out signal RDZ is L-level (inactive), the data terminal DQ becomes high impedance state, and while the read-out signal RDZ is H-level (active), the data terminal DQ becomes the same logic level as the output data signal DOUTZ.
ﾈ郢・所述输出数据信号DOUTZ处于高电平，所述pMOS晶体管P7ｴｪ｣ｬnMOS晶体管N7关闭，以将数据终端DQ设为高电平。ﾈ郢・所述输出数据信号DOUTZ处于低电平，所述pMOS晶体管P7ｹﾘｱﾕ｣ｬnMOS晶体管N7打开，以将数据终端DQ设为低电平。在被提供低电平输出时钟信号CLKOZ时，所述输出数据缓冲器44关闭pMOS晶体管P7ｺﾍnMOS晶体管N7｣ｬﾒﾔ将数据终端DQ设为浮动状态。即，所述读取信号RDZ为低电平（无源）时，所述数据终端DQ变为高阻抗状态，所述读取信号RDZ为高电平（有源）时，所述数据终端DQ变为与输出数据信号DOUTZﾏ猩ｬｵﾄ逻辑电平。
The mode register 18 has a plurality of register regions which are set in accordance with the value of the address signal AINZ received along with the register set signal RSETZ. The mode register 18 outputs a latency signal CASLZ, a burst signal BSTLZ, etc. The value of the latency signal CASLZ denotes latency, which is the number of clock cycles counted from a time when the read command is supplied to a time when the first data is output. The value of the burst signal BSTLZ denotes the number of data pieces which are continually read from the semiconductor memory MEM in response to one read command or the number of data pieces which are continually written into the semiconductor memory MEM in response to one write command. The more register 18 is one example of a register that sets the number of clock cycles as counted from a time when the internal circuit such as the column control unit 36 is started in operation to a time when a data signal is output to a data terminal DQ.
所述模式寄存器18具有多个寄存区域，所述多个寄存区域根据与寄存器设置信号RSETZﾒｻﾆﾓﾊﾕｵﾄｵﾘﾖｷﾐﾅｺﾅAINZｵﾄ值设置。所述模式寄存器18输出延时信号CASLZ｡｢筴ｷ｢信号BSTLZｵﾈ｡｣所述延时信号CASLZｵﾄ值表示等待时间，表示从提供读取命令的时间到输出第一数据的时间统计的时钟周期的数量。所述猝发信号BSTLZｵﾄ值表示响应一个读取命令而从半导体存储器MEM连续读取的数据片的数量或响应一个写入命令而连续写入半导体存储器MEMｵﾄ数据片的数量。所述模式寄存器18是寄存器的一个示例，其对从列控制单元36等内部电路开始运行的时间到数据信号输出给数据终端DQｵﾄ时间统计的时钟周期的数量进行设置。
The latency adjustment circuit CALADJ, the read clock buffer RCLKB, the read data bus switch RDBSW, and the output data latch ODLT operate in a period when the column internal power supply voltage VIIC is generated and stop operations in a period when the internal power supply voltage VIIC is not generated. The output clock control circuit CLKCNT operates as it receives the internal power supply voltage VIIR generated in a period except in the deep power-down mode. The output clock control circuit CLKCNT receives the low-level read signal RDZ in the period when the row internal power supply voltage VIIC is not generated, to set the output clock signal CLKOZ to the low level. The pMOS transistor P7 and the nMOS transistor N7 in the output data buffer 44 are turned off by the low-level output clock signal CLKOZ, so that the data terminal DQ becomes the high impedance state. Accordingly, it is possible to prevent the output data buffer 44 from malfunctioning when the latency adjustment circuit CALADJ, the read clock buffer RCLKB, the read data bus switch RDBSW, and the output data latch ODLT are stopped in operation.
所述等待时间调整电路CALADJ、读取时钟缓冲器RCLKB、读取数据总线开关RDBSW和输出数据锁存器ODLT在生成列内部电源电压VIIC的阶段运行，并在不生成列内部电源电压VIIC的阶段停止运行。所述输出时钟控制电路CLKCNT在接收深度低功耗模式之外的阶段生成的内部电源电压VIIR时运行。所述输出时钟控制电路CLKCNTﾔﾚｲｻﾉ嵭ﾉﾐﾐﾄﾚｲｿｵ釀ｴｵ醵ｹVIICｵﾄ阶段接收低电平读取信号RDZ，以将输出时钟信号CLKOZ设为低电平。所述输出数据缓冲器44中的pMOS晶体管P7和nMOS晶体管N7由低电平输出时钟信号CLKOZ关闭，使数据终端DQ变为高阻抗状态。由此，可ｷﾀﾖｹｵﾈｴﾊｱｼ莊遧酊ｷCALADJ｡｢读取时钟缓冲器RCLKB、读取数据总线开关RDBSW和输出数据锁存器ODLT停止运行时输出数据缓冲器44发生故障。
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Resultaten: 6. Exact: 6. Verstreken tijd: 12 ms.
