Vertaling van "error detection and correction processing" in Chinees
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错误检测和校正处理
Therefore, the present technology addresses the above-identified and other problems associated with related-art methods and apparatuses and solves the addressed problems by providing a storage control apparatus, a storage apparatus, an information processing system, and storage control method that are configured to achieve error detection and correction processing by use of error correcting codes suited to an access size without straining the storage capacity of a nonvolatile memory.
In the related-art technology described above, two types of sizes of units in which access is allowed are arranged in order to execute error detection and correction processing in each of the sizes. However, because this related-art technology generates, in the random access bank, an error correcting code in a data unit smaller than that of the sequential access bank, a capacity occupied by error correcting codes gets relatively large, thereby causing a problem of the deteriorated efficiency of capacity. In this case, if the storage capacity in the random access bank runs short, it is necessary to move part of the data to the sequential access bank, thereby causing a problem of lowered system performance. Generally, in terms of bit cost, the random access bank is several times as large as the sequential access bank, so that increasing the capacity of the random access bank directly increases the system cost.
In order to circumvent this problem, a semiconductor storage apparatus is proposed in which two areas of a bank for executing access in the unit of large-size sector and a bank for executing small-size data length access are arranged to execute error detection and correction processing in each size (refer to Japanese Patent Laid-Open No. 2008-084499 below). With this semiconductor storage apparatus, a bank for sequential access in the unit of sector and a bank for random access in the unit of data are arranged in a NAND-type flash memory.
As described above, according to the embodiment of the present technology, the arrangement of the second ECC buffer 250 allows the execution of error detection and correction processing by use of the first ECC or the second ECC depending on the access size without restricting the storage capacity of the NVM 300. The second ECC buffer 250 has a structure substantially similar to the structure of a cache memory, in which only the second ECC of a necessary capacity is held. Therefore, random access performance can be enhanced without rewriting or frequently accessing the data in the NVM 300. Because the second ECC is large in relative capacity for random access unit, access band may be affected if the second ECC is stored in the NVM 300. According to this embodiment, the storage capacity in the NVM 300 is not restricted. The second ECC buffer 250 can be made up of a nonvolatile memory, the bit cost can be prevented from increasing.
It is a general practice, with the nonvolatile memories mentioned above, to execute error detection and correction processing based on ECC (Error Correcting Code) in order to improve the data retention characteristics. To be more specific, at the writing of data, an error correcting code is computed and the computed error correcting code is recorded to a nonvolatile memory along with the data, and, at the time of reading the data, the data and the error correcting code are read at the same time for bit error detection and correction processing. Assuming the error detection and correction processing like this makes it clear that the matching the unit of error correcting code with the unit of access to a nonvolatile memory is advantageous in performance. If no match is found between both the units, the error detection and correction processing based on an error correcting code is executed, so that a portion other than the data requested for access must also be read, thereby increasing the overhead in access processing.
FIG. 9A shows a first read operation timing. In this case, because the second ECC is not held in the second ECC buffer 250, it is necessary to execute error detection and correction processing by the first ECC after reading the data in the unit of page access from the NVM 300. Therefore, after transferring the data in the unit of page access (for 265 bytes) from the NVM 300 to the data buffer 210 after passing of a read busy interval, error detection and correction processing is executed by the first ECC error detection block 230 and the error correction block 280. Then, the data in the unit of random access (for 32 bytes) from the data in the unit of page access held in the data buffer 210 is transferred to the processor 110.
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