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input data control unit
Vertaling van "input data control unit" in Chinees
输入数据控制单元
The output data buffer 44 operates in the read operation mode, to output the output data signal DOUTZ to the data terminal DQ in response to the output clock signal CLKOZ. An example of the output data buffer 44 is illustrated in FIG. 8. The input data buffer 46 operates in the read operation mode, to output data received at the data terminal DQ to the input data control unit 42 as the input data DINZ.
所述输出数据缓冲器44在读取操作模式下运行，以响应输出时钟信号CLKOZｶ・将输出数据信号DOUTZ输出到数据终端DQ中。所述输出数据缓冲器44的一个示例如图8所示。所述输入数据换充其46在读取操作模式下运行，以将在数据终端DQ接收的数据输出到输入数据控制单元42中，作为输入数据DINZ｡｣
For example, the column control unit 36, the output data control unit 40, and the input data control unit 42 operate as they receive the internal power supply voltages VIIR and VIIC. The memory cell array 38 is not denoted by a thin solid line because it does not directly receive the power supply voltage VDD or the internal power supply voltage VIIR or VIIC.
ﾀﾈ逎ｬ所述列控制单元36、输出数据控制单元40和输入数据控制单元42在接收内部电源电压VIIRｺﾍVIIC时运行。所述存储单元阵列38不用细实线表示，因为其不直接接收电源电压VDDｻﾚｲｿｵ釀ｴｵ醵ｹVIIRｻ・VIIC｡｣
Subsequently, the start-up signal CONX is deactivated in response to the deactivation of the short-circuit signal SWONX, to turn off the pMOS transistor P3 ((k) of FIG. 17). The internal power supply voltage VIIC decreases gradually ((l) of FIG. 17). Then, operations of the column control unit 36B, the output data control unit 40, and the input data control unit 42 which are supplied with the internal power supply voltage VIIC are stopped.
随后，所述启动信号CONXﾏ・ｦ短路信号SWONXｵﾄ停用而停用，以关闭pMOS晶体管P3｣ｨ图17中的（k）｣ｩ｡｣所述内部电源电压VIICﾖ･下降（图17中的（l））。随后，被提供了内部电源电压VIICｵﾄ列控制单元36B、输出数据控制单元40和输入数据控制单元42的操作停止。
The input data control unit 42 operates as it receives the internal power supply voltages VIIR and VIIC. The input data control unit 42 outputs an input data signal DINZ received from the input data buffer 46 to the common data line CDBZ. An example of the input data control unit 42 is illustrated in FIG. 7.
所述输入数据控制单元42在接收内部电源电压VIIRｺﾍVIIC时运行。所述输入数据控制单元42将从输入数据缓冲器46接收的输入数据信号DINZ输出到共用数据线CDBZ中。所述输入数据控制单元42的一个示例如图7所示。
The input data control unit 42 has a write clock buffer WCLKB, an input data latch circuit IDLT, and a write data bus switch WDBSW. FIG. 7 illustrates the input data control unit 42 corresponding to one data terminal DQ (DINZ). The write clock buffer WCLKB generates a write clock signal WCLKZ in synchronization with the clock signal CLKZ when the write signal WRZ is activated at the high level. For example, the write clock signal WCLKZ is activated the number of clock cycles corresponding to a burst length.
所述输入数据控制单元42具有写入时钟缓冲器WCLKB｡｢输入数据锁存电路IDLTｺﾍ写入数据总线开关WDBSW｡｣图7说明了与一个数据终端DQ｣ｨDINZ｣ｩ对应的输入数据控制单元42。所述写入时钟缓冲器WCLKBﾔﾚ写入信号WRZｼ､ｻ鋙ｽ高电平时与时钟信号CLKZ同步生成写入时钟信号WCLKZ｡｣ﾀﾈ逎ｬ所述写入时钟缓冲器WCLKBｼ､ｻ・时，时钟周期的数量与突发长度对应。
For example, the column voltage generation unit 30 is designed such that the internal power supply voltage VIIC may reach the same first voltage V1 as the internal power supply voltage VIIR before the command control unit 16 receives the write command WR or the read command RD. The time T1 is determined by the load capacity of the internal power supply line VIIC and the voltage generation capacity of the column voltage generation unit 30. The internal power supply line VIIC is connected to the column control unit 36, the output data control unit 40, and the input data control unit 42 and has a load capacity smaller than the internal power supply line VIIR. Accordingly, the time T1 is reduced easily. In such a manner, the scale of the circuit supplied with the internal power supply voltage VIIC is determined to satisfy the time T1.
ﾀﾈ逎ｬ所述列电压生成单元30设计为，内部电源电压VIIC可在命令控制单元16接收写入命令WR或读取命令RD之前达到与内部电源电压VIIR相同的第一电压V1。所述时间T1由内部电源电压VIICｵﾄ负荷容量和列电压生成单元30的电压生成能力而确定。所述内部电源电压VIICﾓ・ﾐｿﾘﾖﾆｵ･ﾔｪ36｡｢输出数据控制单元40和输入数据控制单元42连接，其负荷容量小于内部电源电压VIIR｡｣由此，所述时间T1ﾒﾗﾓﾚ缩短。这样，被提供内部电源电压VIICｵﾄ电路的规模一定会满足时间T1｡｣
A period in which the internal power supply voltage VIIC is dissipated owing to the operations of the column control unit 36, the output data control unit 40, and the input data control unit 42 covers a time when the write command WR or the read command RD is received to a time when the write or read operations are completed respectively. By stopping the generation of the internal power supply voltage VIIC in a period when none of the column control unit 36, the output data control unit 40, and the input data control unit 42 operates, the dissipation power of the semiconductor memory MEM is reduced.
内部电源电压VIIC由于ﾁﾐｿﾘﾖﾆ单ﾔｪ36｡｢输出数据控制单元40和输入数据控制单元42的运行而耗散的时间段包括接收写入命令WR或读取命令RD的时间到分别完成写入或读取操作的时间。通过在ﾁﾐｿﾘﾖﾆ单ﾔｪ36｡｢输出数据控制单元40和输入数据控制单元42均不运行期间停止生成内部电源电压VIIC｣ｬ所述半导体存储器MEMｵﾄ耗散功率降低。
If the delay time tDLY is long such that the switch 32 may be turned on after the write command WR or the read command RD is accepted by the command control unit 16, a deficiency may occur in capacity of supplying power to the column control unit 36, the output data control unit 40, and the input data control unit 42 ((f) of FIG. 10). In this case, the internal power supply voltage VIIC drops. Moreover, after the switch 32 is turned on, the internal power supply voltage VIIR drops due to charge sharing. A drop in internal power supply voltage VIIR may affect the operations of the column control unit 36, the output data control unit 40, and the input data control unit 42. For example, the timing at which the input data latch circuit IDLT in the input data control unit 42 illustrated in FIG. 7 latches the input data signal DINZ may possibly shift. Therefore, it is desirable that the switch 32 may be turned on before the column control unit 36, the output data control unit 40, and the input data control unit 42 start to operate, that is, before the write command WR or the read command RD is accepted.
ﾈ郢鋙ﾓｳﾙﾊｱｼ・tDLY较长，使开关32可在命令控制单元16接受写入命令WRｻ・读取命令RD之后打开，向列控制单元36、输出数据控制单元40和输入数据控制单元42提供功率的能力可能会下降（图10中的（f））。这种情况下，所述内部电源电压VIIC下降。另外，在开关32打开之后，所述内部电源电压VIIR由于电荷共享而下降。内部电源电压VIIRｵﾄ下降可能对列控制单元36、输出数据控制单元40和输入数据控制单元42的运行产生影响。例如，图7所示的输入数据控制单元42中的输入数据锁存电路IDLT锁存输入数据信号DINZｵﾄ时间可能会偏移。因此，最好在列控制单元36、输出数据控制单元40和输入数据控制单元42开始运行之前，即，接受写入命令WR或读取命令RD之前打开开关32。
As hereinabove described, the present embodiment provides almost the same effects as those by the earlier described embodiments. Moreover, the switch 32 is turned on after the internal power supply voltage VIIC rises to the first voltage V1 and before the column control unit 36, the output data control unit 40, and the input data control unit 42 start to operate. It is thus possible to prevent fluctuations in internal power supply voltage VIIC, thereby preventing a shift in timing at which the row control unit 34 activates the word line signal WLZ and the sense-amplifier control signal SAEZ. Further, when the switch 32 is turned on, the internal power supply voltage VIIR is supplied to the internal power supply line VIIC, thereby enabling stabilizing the internal power supply voltage VIIC. It is thus possible to prevent a shift in timing at which the input data latch circuit IDLT in the input data control unit 42 latches the input data signal DINZ. That is, it is possible to prevent operations of the column control unit 36, the output data control unit 40, and the input data control unit 42 from being affected.
ﾈ酲ﾏﾋｬｱｾ实施例提供了与前述实施例几乎相同的效果。另外，所述开关32在内部电源电压VIIC升高到第一电压V1之后ｺﾍﾁﾐｿﾘﾖﾆ单ﾔｪ36｡｢输出数据控制单元40和输入数据控制单元42开始运行之前打开。因此，可防止内部电源电压VIIC产生波动，从而防止行控制单元34激活字线信号WLZｺﾍ读出放大器控制信号SAEZｵﾄ时间产生偏移。进一步地，所述开关32打开时，将所述内部电源电压VIIR提供给内部电源电压VIIC｣ｬｴﾓｶｹ内部电源电压VIIC稳定。因此，可防止输入数据控制单元42中的输入数据锁存电路IDLT锁存输入数据信号DINZｵﾄ时间产生偏移。即，可防止ﾁﾐｿﾘﾖﾆ单ﾔｪ36｡｢输出数据控制单元40和输入数据控制单元42的运行受到影响。
The semiconductor memory MEM sequentially receives the write command WR as well as the number of write data pieces WD1, WD2, WD3, and WD4 that corresponds to the burst length, thereby performing write operations ((g) of FIG. 10). When having received the read command RD, the semiconductor memory MEM performs read operations to sequentially output read data pieces RD1, RD2, RD3, and RD4 after the number of clock cycles that corresponds to the latency CASL (CASL=3 in FIG. 10) elapse ((h) of FIG. 10). In the write and read operations, the semiconductor memory MEM starts operating the column control unit 36, the output data control unit 40, and the input data control unit 42 supplied with the internal power supply voltage VIIC after the time tRCD elapses.
所述半导体存储器MEMｰｴﾋｳﾐﾓﾊﾕ写入命令WR以及与突发长度对应的多个写入数据片WD1｡｢WD2｡｢WD3ｺﾍWD4｣ｬｴﾓｶ・进行写入操作（图10中的（g））。接收了读取命令RD之后，所述半导体存储器MEM进行读取操作，以在与等待时间CASL｣ｨ图10中CASL＝3｣ｩ对应的时钟周期数量之后按顺序输出读取数据片RD1｡｢RD2｡｢RD3ｺﾍRD4｡｣ﾔﾚ写入和读取操作中，所述半导体存储器MEMﾔﾚ时间tRCD之后ｿｪﾊｼ运行被提供了内部电源电压VIICｵﾄ列控制单元36、输出数据控制单元40和输入数据控制单元42。
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Resultaten: 10. Exact: 10. Verstreken tijd: 17 ms.
