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memory bandwidth
Vertaling van "memory bandwidth" in Chinees
This means that each 2x2 pixel block writes only 16 bits of edge information, which significantly reduces overall memory bandwidth usage of the algorithm.
这意味着每个 2x2 像素块只可写入 16 比特的边缘信息，从而大幅减少算法的总体内存带宽使用。
However, all the 64-bit objects take up more space, more cache space, more memory bandwidth...
然而，所有的64位对象都会占用更多空间，更多缓存空间，更多内存带宽……
For point lights, adjusting the shadow resolution helps alleviate memory bandwidth bottlenecks as this can be very costly on mobile.
对于点光灯来说，调整阴影分辨率有助于降低内存带宽开销，因为这在移动网络上成本非常之高。
It is trivial to extend this to any other encoding if needed although using an encoding that requires more than 32-bits per color will increase memory bandwidth usage and storage requirements.
将其扩展至任何其他编码并无多大意义，虽然使用需要超过每颜色 32 比特的编码可提高内存带宽使用和存储要求。
Hence, for typical layer configurations, this can result in significant operation written as nested for loops in naïve order, does not leverage the available reuse (weights remaining unchanged across recurrent iterations) and becomes limited by memory bandwidth, thus not utilizing all the available compute on the Intel Xeon Phi processor.
因此，能为典型的层配置带来大量计算。 这个操作是按照原生顺序编写的嵌套循环 ，没有进行重新使用（循环迭代过程中，权重没有变化 ） ， 受内存带宽的限制，因此无法利用英特尔至强融核处理器的全部计算能力。
However, we found no visible gain for Intel Xeon processors - perhaps due to limited memory bandwidth.
然而，我们发现英特尔至强处理器并没有实现明显的性能提升 - 也许是因为内存带宽有限。
AMD EPYC processors with more cores, more memory bandwidth, and more I/O integrate effortlessly with our Supermicro application-optimized platforms to provide leadership performance per-watt and per-dollar to optimize data center TCO.
AMD 的EPYC处理器拥有更多内核、内存带宽以及I/O，能轻松地集成于超微应用优化平台，让每度电和每一元钱都能带来最领先的性能表现，以此来优化数据中心的总拥有成本。
OSB broadcasts snoops when the Intel UPI link is lightly loaded, thus avoiding a directory lookup from memory and reducing memory bandwidth.
当英特尔 UPI 链路处于负载较轻的状态时，OSB 广播开始探听，以避免目录查找内存，降低内存带宽。
Add up to 3TB of DDR4 RAM during initial deployment, or increase memory capacity during the life of your server to meet your business growth. With next generation DDR4 memory support, your overall memory bandwidth increases and is optimized for your workloads.
您最多可以添加3TB的DDR4内存，或在服务器生命周期内增加内存容量以满足业务增长。 借助下一代DDR4内存支持，您的整体内存带宽将会增加并针对您的工作负载进行优化。
Avoiding directory lookup has a direct impact on saving memory bandwidth. Cache Hierarchy Changes
避免目录查找能直接影响内存带宽。 高速缓存结构的变化
Intel Fast Memory Access is an updated Graphics Memory Controller Hub (GMCH) backbone architecture that improves system performance by optimizing the use of available memory bandwidth and reducing the latency of the memory accesses.
英特尔 快速内存访问是图形和内存控制器中枢（GMCH）骨干架构的更新；它通过优化对可用内存带宽的使用和降低内存访问延迟而提高系统性能。
ATI's HYPER ZTM II technology conserves memory bandwidth for improved performance in demanding applications and boosts effective bandwidth by over 25
ATI 的 HYPER ZTM II 技术可节省内存带宽的占用率，以改善高要求应用程序的性能，并将有效带宽提高了 25% 以上
The AMD Embedded R-Series SoC provide single-chip CPU, GPU and I/O controller integration enabling an optimal balance of graphics and compute processing performance without straining memory bandwidth.
AMD 嵌入式 R 系列系统级芯片 （SoC ） 在一块芯片上集成 CPU、GPU 和 I/O 控制器，能够实现图形和计算处理性能的上佳平衡，而不会对内存带宽造成压力。
Synoniemen voor memory bandwidth in het Engels
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