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using fpga
Vertaling van "using fpga" in Chinees
采用FPGA
用FPGA
Accomplish the digital interface with the RF chip and the baseband DSP using FPGA
2．采用FPGA完成与射频芯片及基带DSP之间数字接口；
This system adopts the image content comparison system based on hardware ICS and audio features comparison system as the core of ACS, ICS and ACS for anhui modern developed using FPGA and digital processing all the hardware of image and audio feature extraction module.
本系统采用基于硬件的图像内容比对系统ICS和音频特征比对系统ACS为核心，ICS和ACS均为安徽现代研制的采用FPGA和数字处理的全硬件图像和音频特征提取比对模块。
D, using FPGA to realize heterogeneous computing technology
d、用FPGA实现异构计算的技术；
An implementation build-in PLC method using FPGA is put forward.
提出了一种用FPGA实现数控系统内置式PLC的方法。
Using FPGA programmable logic circuit XC3S200A, run faster, more stable system
采用FPGA可编程逻辑电路XC3S200A，运行速度更快，系统更稳定；
Introducing Synergy Core - Antelope Audio's next generation signal processing platform. Using FPGA's massive parallel computation capabilities and industry-standard DSP power combined, Synergy Core frees up your CPU while processing your FX with extremely low latency.
I让我们来介绍Synergy Core协同核心 - 羚羊音频的下一代音频信号处理平台。采用FPGA强大的并行计算能力并结合行业标准的DSP功能，Synergy Core可在极低延迟的情况下处理音频效果，而不占用CPU资源。
More attractive thing is that using FPGA can integrate board product in chip product, so as to reduce power consumption, realize the application of FPGA in the low-speed, low power consumption system.
更吸引人的是采用FPGA 器件可以将原来的电路板级产品集成为芯片级产品，从而降低了功耗，尝试了FPGA在低功耗、低数据率系统的应用。
Base-band I, Q random data of radar clutter can be produced in real-time by using FPGA, and intermediate-frequency analogue interference signals of radar clutter can be produced by DUC.
利用FPGA等实时产生出的雷达杂波基带I、Q随机数序列，经过数字正交上变频器即可产生出雷达杂波中频模拟干扰信号。
A control strategy based on BP-PID was introduced to decouple the looper system by using FPGA, which includeds systolic mapping, data representation and precision, and computation components design.
采用基于BP神经网络整定的PID控制策略以减弱系统的耦合影响，并给出了其控制算法在FPGA上实现的方法，包括脉动阵列算法映射、数据表示及精度和运算部件设计。
The implementation of the general SDH device timing is introduced in this paper, which includes extracting timing signal, timing mode and controlling the SSM of signal using FPGA.
本文讨论了一般的SDH设备的定时信号的提取，定时的工作方式，以及利用FPGA对SSM控制来实现定时的方案。
Implementation of a full search block matching algorithm using FPGA
一种全搜索块匹配算法的FPGA实现及其应用
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Synoniemen voor using fpga in het Engels
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