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デバッグ環境
The commands sent by the debugger should give the debugger enough control to display the current debug environment and state.
Using a powerful interactive graphical debug environment, RTL designers (especially those new to power) can easily and efficiently debug power hotspots.
Synopsys' Verdi Advanced AMS Debug provides comprehensive views of the overall design and enables seamless debug for co-simulation of analog, digital and mixed-signal subsystems within a unified debug environment.
The USB 3.1 VIP supports Verdi Protocol Analyzer, a protocol-centric debug environment that substantially increases user productivity with protocol-aware features to simplify viewing and debug of complex protocols.
Verdi Protocol Analyzerは、複雑なプロトコル動作の可視化とデバッグを容易にするプロトコル・アウェア機能により検証エンジニアの生産性を大幅に向上させるプロトコル・セントリックなデバッグ環境である。
Synopsys memory VIP is integrated with Synopsys' protocol-aware debug environment, extending the functionality of Verdi Protocol Analyzer to support memory-centric debug features.
Verdi Protocol Analyzer, available with the VC Verification IP (VIP) portfolio, is a simulator independent, protocol and memory aware debug environment that enables users to quickly debug with any verification environment and easily share simulation results across teams.
This combination gives a complete hardware development environment which includes an Integrated Debug Environment, Compiler, and full hardware debugging and Trace capability on selected TI microcontrollers, processors and wireless connectivity microcontrollers.
As with the HAPS DTD flow, the system state can then be downloaded and written into VCD file or FSDB database for further debugging in the chosen off-line debug environment.
Mon-Ren Chene, S2C's Chairman and CTO said: our vision when we founded S2C was to provide a complete FPGA prototyping environment including both hardware and software in order to create an efficient and productive FPGA-based prototyping design and debug environment.
Complex Power State Table Debug: Related to hierarchical power state analysis, VC LP provides users the ability to understand and if necessary, debug the resulting complex power state tables.Powerful Verdi-based Debug: Low power violations in VC LP can be visualized, analyzed and debugged in the familiar and intuitive Verdi power-aware debug environment.
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