English

Arabic Catalan Chinese Czech Danish Dutch English French German Greek Hebrew Hindi Hungarian Italian Japanese Korean Persian Polish Portuguese Romanian Russian Slovak Spanish Swedish Thai Turkish Ukrainian Vietnamese

Chinese

Definition Arabic Catalan Chinese Czech Danish Dutch English French German Greek Hebrew Hindi Hungarian Italian Japanese Korean Persian Polish Portuguese Romanian Russian Slovak Spanish Swedish Thai Turkish Ukrainian Vietnamese

Favorites

Advertising

data buffer

Definition

temporary storage area that holds digital information while it is transferred ... See more

Translation of "data buffer" in Chinese

Definition NEW

数据缓冲器

数据缓冲

数据缓冲区

The size of the data read from the NVM 300 is in the unit of page size, so that the second ECC generation block 240 divides the data in the unit of random access, generates a second ECC for each of the divided data, and outputs the resultant data to the second ECC buffer 250. From the data in the unit of page access held in the data buffer 210, the data in the unit of random access to be read is transferred to the processor 110.

从NVM 300读取的数据的量以页数为单位，因此，第二ECC生成块240以随机存取为单位分割数据，为每个分割数据生成第二ECC，并将结果数据输出给第二ECC缓冲器250。在保留在数据缓冲器210中的以分页存取为单位的数据中，将读取的以随机存取为单位的数据传输给处理器110。

In this first read operation, the second ECC is generated in the second ECC generation block 240 concurrently with the transfer to the data buffer 210. In the assumed example, 256-byte data is read in the unit of page access, so that eight second ECCs are generated on a 32-byte basis.

ﾔﾚ该第一读取操作中，在传输给数据缓冲器210的同时，第二ECC生成块240生成第二ECC。在假定示例中，256字节以分页存取为单位读取，从而基于32字节生成八个第二ECC。

Select the data buffer size you want to use.

请选择您要使用的数据缓冲大小。

The disadvantages of using resynchronization of high speed signalling are (i) increased chip complexity, area, power consumption, and cost, and (ii) increased delay through the isolator chip due to the necessary transmit data buffer.

使用高速信令再同步的缺点在于，（i）增加了芯片复杂性、面积、功耗和成本；（ii）由于必要的传输数据缓冲，增加了经过隔离器芯片时的延迟。

In the coding of the program, every step is same as in previous program except the data buffer dbuf2, which we are using to handle the error generated by bad sector during the Disk reading operation and to maintain the size of the image file.

对编码方案：在编码方案的每一步同以往计划除了数据缓冲dbuf2（512 ），我们以处理错误造成恶劣部门在阅读器的运作，维持人数影像档.

Multi-functional data buffer compilation, supporting direct modification by keyboard, and copying, filling and logical operation. Supports hex and ASCII displays

多功能数据缓冲编辑功能，支持键盘直接修改，支持复制、填充、逻辑运算。支持十六进制显示和ASCII显示

The Keysight N6761A is a 50 W precision DC power module that provides low noise, and precise control and measurements in the milliampere and microampere region with the ability to simultaneously digitize voltage and current, and capture those measurements in an oscilloscope-like data buffer.

描述 Keysight N6761A 是一款 50 W 精密型直流电源模块，可提供低噪声特性、毫安级和微安级的精密控制与测量功能，并且能够同时对电压和电流进行数字化处理，并在类似于示波器的数据缓冲器中捕获这些测量值。

The first ECC generation block 220 generates a first error correcting code (ECC) for the data held in the data buffer 210 in a write operation. The first ECC generated by the first ECC generation block 220 is stored in the NVM 300 as related with the data. Therefore, it is desired that this first ECC be an error correcting code for encoding on an access basis in the NVM 300. In addition, a BCH code may be used for the first ECC. It should be noted that, because an error correcting code has a function of error detection, the error correcting code may also be referred to as an error detection code. It should be noted that the first ECC generation block 220 is one example of a first error detection code generation block cited in the scope of claims herein.

ﾋﾚﾒｻECC生成块220为写入操作中保留在数据缓冲器210中的数据生成第一错误校正码（ECC）。ﾋﾚﾒｻECC生成块220生成的第一ECC存储于与所述数据相关的NVM 300中。因此，该第一ECC应为用于基于存取编码到NVM 300中的错误校正码。另外，BCH编码可用于第一ECC。应注意的是，由于错误校正码具有错误检测的功能，所述错误校正码还可称为错误检测码。应注意的是，所述第一ECC生成块220是本文的权利要求的范围内所述的第一错误检测码生成块的一个示例。

The input data control unit 42 operates as it receives the internal power supply voltages VIIR and VIIC. The input data control unit 42 outputs an input data signal DINZ received from the input data buffer 46 to the common data line CDBZ. An example of the input data control unit 42 is illustrated in FIG. 7.

所述输入数据控制单元42在接收内部电源电压VIIRｺﾍVIIC时运行。所述输入数据控制单元42将从输入数据缓冲器46接收的输入数据信号DINZ输出到共用数据线CDBZ中。所述输入数据控制单元42的一个示例如图7所示。

Acquisition of signals through direct access to theÂ INCA data buffer

通过直接访问INCA数据缓冲器采集信号

On the basis of the data and the first ECC read from the NVM 300, the first ECC error detection block 230 detects an error in the data and the error correction block 280 corrects the detected error (step S922). The error-corrected data is held in the data buffer 210. Concurrently, the second ECC generation block 240 generates the second ECC for the data read from the NVM 300 (step S923). The second ECC thus generated is held in the second ECC buffer 250 (step S924). Because page access unit is greater than random access unit in which encoding is executed by the second ECC, the second ECC generation processing is repeated in order to generate two or more second ECCs (step S925). In an assumed example, 256-byte data is read by page access, so that eight second ECCs are generated on a 32 byte basis.

根据从NVM 300读取的数据和第一ECC，所述第一ECC错误检测块230检测数据中的错误，所述错误校正块280对检测的错误进行校正（步骤S922）。校正了错误的数据保留在数据缓冲器210中。同时，所述第二ECC生成块240为从从NVM 300读取的数据生成第二ECC（步骤S923）。这样生成的第二ECC保留在第二ECC缓冲器250中（步骤S924）。由于分页存取单位大于由第二ECC执行编码的随机存取单位，重复第二ECC生成处理，以生成两个或多个第二ECC（步骤S925）。在假定示例中，通过分页存取读取256字节数据，从而基于32字节生成八个第二ECC。

As described above, for the data in the data buffer 210 with the write data reflected, the first ECC generation block 220 generates the first ECC (step S933). Concurrently, the second ECC in the second ECC buffer 250 is updated. Namely, if the second ECC corresponding to the data to be written is found in the second ECC buffer 250 (step S934), then the second ECC generation block 240 generates the second ECC in the unit of random access (step S935). The generated second ECC is held in the second ECC buffer 250 to be updated (step S936). If the second ECC has not been generated for all data to be written, the second ECC generation processing is repeated until all the second ECCs are generated (step S937).

ﾈ酲ﾏﾋｬ对于具有反射的写入数据的数据缓冲器210中的数据，第一ECC生成块220生成第一ECC（步骤S933）。同时，更新第二ECC缓冲器250中的第二ECC。即，如果第二ECC缓冲器250中发现与将写入的数据对应的第二ECC（步骤S934），所述第二ECC生成块240生成以随机存取为单位的第二ECC（步骤S935）。生成的第二ECC保留在第二ECC缓冲器250中，以进行更新（步骤S936）。如果没有对将写入的所有数据生成第二ECC，重复第二ECC生成处理，知道生成所有第二ECC（步骤S937）。

If the output data signal DOUTZ is at the high level, the pMOS transistor P7 is turned on and the nMOS transistor N7 is turned off to set the data terminal DQ to the high level. If the output data signal DOUTZ is at the low level, the pMOS transistor P7 is turned off and the nMOS transistor N7 is turned on to set the data terminal DQ to the low level. If supplied with the low-level output clock signal CLKOZ, the output data buffer 44 turns off the pMOS transistor P7 and the nMOS transistor N7 to set the data terminal DQ into the floating state. That is, while the read-out signal RDZ is L-level (inactive), the data terminal DQ becomes high impedance state, and while the read-out signal RDZ is H-level (active), the data terminal DQ becomes the same logic level as the output data signal DOUTZ.

ﾈ郢・所述输出数据信号DOUTZ处于高电平，所述pMOS晶体管P7ｴｪ｣ｬnMOS晶体管N7关闭，以将数据终端DQ设为高电平。ﾈ郢・所述输出数据信号DOUTZ处于低电平，所述pMOS晶体管P7ｹﾘｱﾕ｣ｬnMOS晶体管N7打开，以将数据终端DQ设为低电平。在被提供低电平输出时钟信号CLKOZ时，所述输出数据缓冲器44关闭pMOS晶体管P7ｺﾍnMOS晶体管N7｣ｬﾒﾔ将数据终端DQ设为浮动状态。即，所述读取信号RDZ为低电平（无源）时，所述数据终端DQ变为高阻抗状态，所述读取信号RDZ为高电平（有源）时，所述数据终端DQ变为与输出数据信号DOUTZﾏ猩ｬｵﾄ逻辑电平。