Beside that, the main scientific question is the construction of such a data structure under a 'Two-Level Memory Model' with small main storage.
Die hauptsächliche wissenschaftliche Fragestellung ist die Konstruktion einer solchen Datenstruktur unter einem 'Two-Level-Memory Model' mit geringem Hauptspeicher.
Finite state automaton text search apparatus having two-level memory structure.
Andere resultaten
Apparatus and method for reducing interference in two-level cache memories.
A memory according to claim 1, wherein said two levels of memory hierarchy comprise a cache at L1 and a main memory at L2.
A memory according to claim 1, wherein said at least two levels of memory comprise a three level memory hierarchy with a level 1 cache at L1, a level 2 cache at L2 and a main memory at level 3 (L3).
INTEGRATED LEVEL TWO CACHE AND MEMORY CONTROLLER WITH MULTIPLE DATA PORTS
SIX-INPUT MULTIPLEXER WITH TWO GATE LEVELS AND THREE MEMORY CELLS
The node as recited in claim 6, wherein said processor device (38A) further comprises a SPARC processor and a level two cache memory coupled to said SPARC processor.
Knoten nach Anspruch 6, wobei die Prozessoreinrichtung (38A) weiterhin einen SPARC-Prozessor und einen Level-two-Cachespeicher aufweist, der mit dem SPARC-Prozessor verbunden ist.
What, two megabytes of level two cache memory?
Static memory cell having electrical elements on two levels.
EEPROM memory cell with two levels of polysilicon and a tunnel oxide zone.
Security policies that allow you to configure memory protection on two levels
A method to reduce memory latencies by performing two levels of speculation